1. Field of the Invention
The present invention relates to a precharge control signal generating circuit of a semiconductor device, particularly of a semiconductor memory operating at a low voltage.
2. Description of the Related Art
In a semiconductor memory, a large number of memory cells storing data are arranged and connected in a matrix form by a bit line pair (paired two bit lines) in a column direction and a word line in a row direction. This bit line pair is equalized to a predetermined precharge voltage by a precharge control circuit during a precharge period. The precharge control circuit is controlled by a precharge control signal. The details are disclosed in, for example, Japanese Patent Application Laid-open No. Hei. 6-68666.
The foregoing conventional technique has the following problem to be solved.
When a power source voltage of a semiconductor memory is designed to be low, a potential difference between a gate and a source of an NMOS transistor constituting the precharge control circuit becomes small. As a result, there remains a problem to be solved that the NMOS transistor becomes hard to turn on, and a time required to equalize the bit line pair becomes long.